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? semiconductor components industries, llc, 2006 february, 2006 ? rev. 7 1 publication order number: mc10e016/d mc10e016, mc100e016 5.0 vecl 8?bit synchronous binary up counter description the mc10e/100e016 is a high ? speed synchronous, presettable, cascadable 8 ? bit binary counter. architecture and operation are the same as the mc10h016 in the mecl 10h ? family, extended to 8 ? bits, as shown in the logic symbol. the counter features internal feedback of tc , gated by the tcld (terminal count load) pin. when tcld is low (or left open, in which case it is pulled low by the internal pull ? downs), the tc feedback is disabled, and counting proceeds continuously, with tc going low to indicate an all ? one state. when tcld is high, the tc feedback causes the counter to automatically reload upon tc = low, thus functioning as a programmable counter. the q n outputs do not need to be terminated for the count function to operate properly. to minimize noise and power, unused q outputs should be left unterminated. the 100 series contains temperature compensation. features ? 700 mhz min. count frequency ? 1000 ps clk to q, tc ? internal tc feedback (gated) ? 8 ? bit ? fully synchronous counting and tc generation ? asynchronous master reset ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ? 4.2 v to ? 5.7 v ? pb ? free packages are available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram* xxx = 10 or 100 a = assembly location wl = wafer lot yy = year ww = work week g= pb ? free package plcc ? 28 fn suffix case 776 mcxxxe016g awlyyww 1 http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information
mc10e016, mc100e016 http://onsemi.com 2 1 mr clk tcld v ee nc p 0 p 1 26 27 28 2 3 4 25 24 23 22 21 20 1 9 18 17 16 15 14 13 12 11 5678910 pe ce p 7 p 6 p 5 v cco tc q 7 q 6 v cc q 5 q 4 q 3 p 2 p 3 p 4 v cco q 0 q 1 q 2 v cco figure 1. 28 ? lead pinout assignment (top view) all v cc and v cco pins are tied together on the die. warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. table 1. pin description pin function p0 ? p 7 q 0 ? q 7 ce pe mr clk tc tcld nc v cc , v cco v ee ecl parallel data (preset) inputs ecl data outputs ecl count enable control input ecl parallel load enable control input ecl master reset ecl clock ecl terminal count output ecl tc ? load control input no connect positive supply negative supply figure 2. 8 ? bit binary counter logic counter note that this diagram is provided for understanding of logic operation only. it should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. p 1 slave master 5 tc q 1 q 0 p7 q 6 q 5 q 4 q 3 q 2 q 1 ce q 0 bit 1 ce q 0 q0m q0m bit 0 pe tcld ce po mr clk bit 7 bits 2?6 q 7 table 2. function table function ce pe tcld mr clk load parallel (p n to q n ) x l x l z continuous count l h l l z count; load parallel on tc = low l h h l z hold h h x l z masters respond, slaves hold x x x l zz reset (q n : = low, tc : = high) x x x h x z = clock pulse (low to high); zz = clock pulse (high to low)
mc10e016, mc100e016 http://onsemi.com 3 table 3. expanded function table function pe ce mr tcld clk p7 ? p4 p3 p2 p1 p0 q7 ? q4 q3 q2 q1 q0 tc load l x l x z h h h l l h h h l l h count h ll l z x xxxx h hhlhh h ll l z x xxxx h hhhlh h ll l z x xxxx h hhhhl h ll l z x xxxx l llllh load l xl x z h hhl l h hhl lh hold h hl x z x xxxx h hhl lh h hl x z x xxxx h hhl lh load on h ll h z h lhhl h hhlhh terminal h ll h z h lhhl h hhhlh count h ll h z h lhhl h hhhhl h ll h z h lhhl h lhhlh h ll h z h lhhl h lhhhh h ll h z h lhhl h hlllh reset x x h x x x x x x x l l l l l h table 4. attributes characteristics value internal input pulldown resistor 50 k internal input pullup resistor 50 k esd protection human body model machine model > 2 kv > 200 v moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb ? free pkg plcc ? 28 level 1 level 3 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 592 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc10e016, mc100e016 http://onsemi.com 4 table 5. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 8 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ? 6 v i out output current continuous surge 50 100 ma ma t a operating temperature range 0 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm plcc ? 28 plcc ? 28 63.5 43.5 c/w c/w jc thermal resistance (junction ? to ? case) standard board plcc ? 28 22 to 26 c/w t sol wave solder pb pb ? free 265 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. table 6. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 151 181 151 181 151 181 ma v oh output high voltage (note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv i ih input high current 150 150 150 a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. input and output parameters vary 1:1 with v cc . v ee can vary ? 0.46 v / +0.06 v. 2. outputs are terminated through a 50 resistor to v cc ? 2.0 v.
mc10e016, mc100e016 http://onsemi.com 5 table 7. 10e series necl dc characteristics v ccx = 0.0 v; v ee = ? 5.0 v (note 3) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 151 181 151 181 151 181 ma v oh output high voltage (note 4) ? 1020 ? 930 ? 840 ? 980 ? 895 ? 810 ? 910 ? 815 ? 720 mv v ol output low voltage (note 4) ? 1950 ? 1790 ? 1630 ? 1950 ? 1790 ? 1630 ? 1950 ? 1773 ? 1595 mv v ih input high voltage ? 1170 ? 1005 ? 840 ? 1130 ? 970 ? 810 ? 1060 ? 890 ? 720 mv v il input low voltage ? 1950 ? 1715 ? 1480 ? 1950 ? 1715 ? 1480 ? 1950 ? 1698 ? 1445 mv i ih input high current 150 150 150 a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. input and output parameters vary 1:1 with v cc . v ee can vary ? 0.46 v / +0.06 v. 4. outputs are terminated through a 50 resistor to v cc ? 2.0 v. table 8. 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 5) symbol characteristic 0 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 151 181 151 181 174 208 ma v oh output high voltage (note 6) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 6) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage 3835 3975 4120 3835 3975 4120 3835 3975 4120 mv v il input low voltage 3190 3355 3525 3190 3355 3525 3190 3355 3525 mv i ih input high current 150 150 150 a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . v ee can vary ? 0.46 v / +0.8 v. 6. outputs are terminated through a 50 resistor to v cc ? 2.0 v.
mc10e016, mc100e016 http://onsemi.com 6 table 9. 100e series necl dc characteristics v ccx = 0.0 v; v ee = ? 5.0 v (note 7) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 151 181 151 181 174 208 ma v oh output high voltage (note 8) ? 1025 ? 950 ? 880 ? 1025 ? 950 ? 880 ? 1025 ? 950 ? 880 mv v ol output low voltage (note 8) ? 1810 ? 1705 ? 1620 ? 1810 ? 1745 ? 1620 ? 1810 ? 1740 ? 1620 mv v ih input high voltage ? 1165 ? 1025 ? 880 ? 1165 ? 1025 ? 880 ? 1165 ? 1025 ? 880 mv v il input low voltage ? 1810 ? 1645 ? 1475 ? 1810 ? 1645 ? 1475 ? 1810 ? 1645 ? 1475 mv i ih input high current 150 150 150 a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. input and output parameters vary 1:1 with v cc . v ee can vary ? 0.46 v / +0.8 v. 8. outputs are terminated through a 50 resistor to v cc ? 2.0 v. table 10. ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = ? 5.0 v (note 9) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency 700 700 700 mhz f count maximum count frequency 700 900 700 900 700 900 mhz t plh , t phl propagation delay to output ps clk to q 500 725 900 500 725 900 500 725 900 mr to q 500 775 900 500 775 900 500 775 900 clk to tc 500 775 900 500 775 900 500 775 900 mr to tc 500 775 900 500 775 900 500 775 900 t s setup time (to clk +) ps pn 150 ? 30 150 ? 30 150 ? 30 ce 600 400 600 400 600 400 pe 600 400 600 400 600 400 tcld 500 300 500 300 500 300 t h hold time (to clk +) pn 350 100 350 100 350 100 ce 400 200 400 200 400 200 pe 0 200 0 200 0 200 tcld 100 ? 300 100 ? 300 100 ? 300 t rr reset recovery time 900 700 900 700 900 700 ps t pw minimum pulse width ps clk, mr 400 400 400 t jitter random clock jitter (rms) < 1 < 1 < 1 ps t r , t f rise/fall times (20 ? 80%) 200 510 700 200 510 700 200 510 700 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. 10 series: v ee can vary ? 0.46 v / +0.06 v. 100 series: v ee can vary ? 0.46 v / +0.8 v.
mc10e016, mc100e016 http://onsemi.com 7 applications information cascading multiple e016 devices for applications which call for larger than 8 ? bit counters multiple e016s can be tied together to achieve very wide bit width counters. the active low terminal count (tc ) output and count enable input (ce ) greatly facilitate the cascading of e016 devices. two e016s can be cascaded without the need for external gating, however for counters wider than 16 bits external or gates are necessary for cascade implementations. figure 3 below pictorially illustrates the cascading of 4 e016s to build a 32 ? bit high frequency counter. note the e101 gates used to or the terminal count outputs of the lower order e016s to control the counting operation of the higher order bits. when the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state) the more significant e016 is set in its count mode and will count one binary digit upon the next positive clock transition. in addition, the preceding devices will also count one bit thus sending their terminal count outputs back to a high state disabling the count operation of the more significant counters and placing them back into hold modes. therefore, for an e016 in the chain to count, all of the lower order terminal count outputs must be in the low state. the bit width of the counter can be increased or decreased by simply adding or subtracting e016 devices from figure 3 and maintaining the logic pattern illustrated in the same figure. the maximum frequency of operation for the cascaded counter chain is set by the propagation delay of the tc output and the necessary setup time of the ce input and the propagation delay through the or gate controlling it (for 16 ? bit counters the limitation is only the tc propagation delay and the ce setup time). figure 3 shows el01 gates used to control the count enable inputs, however, if the frequency of operation is lower a slower, ecl or gate can be used. using the worst case guarantees for these parameters from the eclinps data book, the maximum count frequency for a greater than 16 ? bit counter is 500 mhz and that for a 16 ? bit counter is 625 mhz. note that this assumes the trace delay between the tc outputs and the ce inputs are negligible. if this is not the case estimates of these delays need to be added to the calculations. figure 3. 32 ? bit cascaded e016 counter el01 clock p0 ?> p7 tc clk p0 ?> p7 tc clk el01 p0 ?> p7 tc clk p0 ?> p7 msb e016 pe ce q0 ?> q7 q0 ?> q7 q0 ?> q7 e016 pe ce q0 ?> q7 e016 pe ce lsb e016 pe ce lo load tc clk
mc10e016, mc100e016 http://onsemi.com 8 applications information (continued) programmable divider the e016 has been designed with a control pin which makes it ideal for use as an 8 ? bit programmable divider. the tcld pin (load on terminal count) when asserted reloads the data present at the parallel input pin (pn? s) upon reaching terminal count (an all 1s state on the outputs). because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. figure 4 below illustrates the input conditions necessary for utilizing the e016 as a programmable divider set up to divide by 113. h l h hlllhhhh tc pe ce tcld clk p7 p6 p4 p3 p2 p1 p0 p5 q7 q6 q4 q3 q2 q1 q0 q5 figure 4. mod 2 to 256 programmable divider to determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio from the binary value for 256. as an example for a divide ratio of 113: pn?s = 256 ? 113 = 8f 16 = 1000 1111 where: p0 = lsb and p7 = msb forcing this input condition as per the setup in figure 4 will result in the waveforms of figure 5. note that the tc output is used as the divide output and the pulse duration is equal to a full clock period. for even divide ratios, twice the desired divide ratio can be loaded into the e016 and the tc output can feed the clock input of a toggle flip flop to create a signal divided as desired with a 50% duty cycle. table 11. preset values for various divide ratios divide ratio preset data inputs p7 p6 p5 p4 p3 p2 p1 p0 2 h h h h h h h l 3 h hhhhhlh 4 h hhhhhl l 5 h hhhhlhh w w ??????? w ? ??????? 112 h llhllll 113 h l l lhhhh 114 h l l lhhh l ? ? ??????? ? ? ??????? 254 l lllllhl 255 l llllllh 256 l l l l l l l l a single e016 can be used to divide by any ratio from 2 to 256 inclusive. if divide ratios of greater than 256 are needed multiple e016s can be cascaded in a manner similar to that already discussed. when e016s are cascaded to build larger dividers the tcld pin will no longer provide a means for loading on terminal count. because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the tc pins must be used for multiple e016 divider chains. ??? pe ??? ??? clock tc load divide by 113 load 1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111 figure 5. divide by 113 e016 programmable divider waveforms
mc10e016, mc100e016 http://onsemi.com 9 applications information (continued) e016 msb clk tc pe ce e016 clk tc pe ce e016 clk tc pe ce el01 el01 el01 clock q0 ?> q7 po ?> p7 q0 ?> q7 po ?> p7 q0 ?> q7 po ?> p7 q0 ?> q7 po ?> p7 lo e016 lsb clk tc pe ce figure 6. 32 ? bit cascaded e016 programmable divider out figure 6 shows a typical block diagram of a 32 ? bit divider chain. once again to maximize the frequency of operation el01 or gates were used. for lower frequency applications a slower or gate could replace the el01. note that for a 16 ? bit divider the or function feeding the pe (program enable) input cannot be replaced by a wire or tie as the tc output of the least significant e016 must also feed the ce input of the most significant e016. if the two tc outputs were or tied the cascaded count operation would not operate properly. because in the cascaded form the pe feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device. maximizing e016 count frequency the e016 device produces 9 fast transitioning single ? ended outputs, thus v cc noise can become significant in situations where all of the outputs switch simultaneously in the same direction. this v cc noise can negatively impact the maximum frequency of operation of the device. since the device does not need to have the q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system they should be left unterminated. in addition, if only a subset of the q outputs are used in the system only those outputs should be terminated. not terminating the unused outputs will not only cut down the v cc noise generated but will also save in total system power dissipation. following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published data book specifications.
mc10e016, mc100e016 http://onsemi.com 10 figure 7. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package type shipping ? mc10e016fn plcc ? 28 37 units/rail mc10e016fng plcc ? 28 (pb ? free) 37 units/rail mc10e016fnr2 plcc ? 28 500 units/reel mc10e016fnr2g plcc ? 28 (pb ? free) 500 units/reel mc100e016fn plcc ? 28 37 units/rail mc100e016fng plcc ? 28 (pb ? free) 37 units/rail MC100E016FNR2 plcc ? 28 500 units/reel MC100E016FNR2g plcc ? 28 (pb ? free) 500 units/reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc10e016, mc100e016 http://onsemi.com 11 package dimensions plcc ? 28 fn suffix plastic plcc package case 776 ? 02 issue e 0.007 (0.180) tl ?m s n s m 0.007 (0.180) tl ?m s n s m 0.007 (0.180) tl ?m s n s m 0.010 (0.250) tl ?m s n s s 0.007 (0.180) tl ?m s n s m 0.010 (0.250) tl ?m s n s s 0.007 (0.180) tl ?m s n s m 0.007 (0.180) tl ?m s n s m 0.004 (0.100) seating plane ? t ? 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 2 10.42 1.02 12.57 12.57 4.57 2.79 0.48 0.81 11.58 11.58 1.21 1.21 1.42 0.50 10 10.92 1.27 bsc a b c e f g h j k r u v w x y z g1 k1 min min max max inches millimeters dim notes: 1. datums ?l?, ?m?, and ?n? determined where top of lead shoulder exits plastic body at mold parting line. 2. dim g1, true position to be measured at datum ?t?, seating plane. 3. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). view s b u z g1 x view d ? d h k f view s g c z a r e j 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 2 0.410 0.040 0.495 0.495 0.180 0.110 0.019 0.032 0.456 0.456 0.048 0.048 0.056 0.020 10 0.430 0.050 bsc ? n ? y brk d d w ? m ? ? l ? 28 1 v g1 k1
mc10e016, mc100e016 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 mc10e106/d mecl is a trademark of motorola, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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